Wafer level package with good cte performance

ABSTRACT

The present invention provides a structure of package comprising a substrate with a pre-formed die receiving cavity formed and/or terminal contact metal pads formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. At least one re-distribution built up layer (RDL) is formed on the dielectric layer and coupled to the die via contact pad. Connecting structure, for example, UBM is formed over the redistribution built up layer. Terminal Conductive bumps are coupled to the UBM.

FIELD OF THE INVENTION

This invention relates to a structure of wafer level package (WLP), andmore particularly to a wafer level package with good CTE performance.

DESCRIPTION OF THE PRIOR ART

In the field of semiconductor devices, the device density is increasedand the device dimension is reduced, continuously. The demand for thepackaging or interconnecting techniques in such high density devices isalso increased to fit the situation mentioned above. Conventionally, inthe flip-chip attachment method, an array of solder bumps is formed onthe surface of the die. The formation of the solder bumps may be carriedout by using a solder composite material through a solder mask forproducing a desired pattern of solder bumps. The function of chippackage includes power distribution, signal distribution, heatdissipation, protection and support . . . and so on. As a semiconductorbecome more complicated, the traditional package technique, for examplelead frame package, flex package, rigid package technique, can't meetthe demand of producing smaller chip with high density elements on thechip.

Furthermore, because conventional package technologies have to divide adice on a wafer into respective dies and then package the dierespectively, therefore, these techniques are time consuming formanufacturing process. Since the chip package technique is highlyinfluenced by the development of integrated circuits, therefore, as thesize of electronics has become demanding, so does the package technique.For the reasons mentioned above, the trend of package technique istoward ball grid array (BGA), flip chip (FC-BGA), chip scale package(CSP), Wafer level package (WLP) today. “Wafer level package” is to beunderstood as meaning that the entire packaging and all theinterconnections on the wafer as well as other processing steps arecarried out before the singulation (dicing) into chips (dies).Generally, after completion of all assembling processes or packagingprocesses, individual semiconductor packages are separated from a waferhaving a plurality of semiconductor dies. The wafer level package hasextremely small dimensions combined with extremely good electricalproperties.

WLP technique is an advanced packaging technology, by which the die aremanufactured and tested on the wafer, and then singulated by dicing forassembly in a surface-mount line. Because the wafer level packagetechnique utilizes the whole wafer as one object, not utilizing a singlechip or die, therefore, before performing a scribing process, packagingand testing has been accomplished; furthermore, WLP is such an advancedtechnique so that the process of wire bonding, die mount and under-fillcan be omitted. By utilizing WLP technique, the cost and manufacturingtime can be reduced, and the resulting structure of WLP can be equal tothe die; therefore, this technique can meet the demands ofminiaturization of electronic devices.

Though the advantages of WLP technique mentioned above, some issuesstill exist influencing the acceptance of WLP technique. For instance,the CTE difference (mismatching) between the materials of a structure ofWLP becomes another critical factor to mechanical instability of thestructure. A package scheme disclosed by Intel patent number U.S. Pat.No. 6,271,469 suffers the CTE mismatching issue. It is because the priorart uses silicon die encapsulated by molding compound. As known, the CTEof silicon material is 2.3, but the CTE of molding compound is around20-40. The arrangement causes chip location be shifted during processdue to the curing temperature of compound and dielectric layersmaterials are higher and the inter-connecting pads will be shifted thatwill causes yield and performance problem. It is difficult to return theoriginal location during temperature cycling (it caused by the epoxyresin property if the curing Temp near/over the Tg). It means that theprior structure package can not be processed by large size, and itcauses higher manufacturing cost.

Further, some technical involves the usage of die that directly formedon the upper surface of the substrate. As known, the pads of thesemiconductor die will be redistributed through redistribution processesinvolving a redistribution layer (RDL) into a plurality of metal pads inan area array type. The build up layer will increase the size of thepackage. Therefore, the thickness of the package is increased. This mayconflict with the demand of reducing the size of a chip.

Further, the prior art suffers complicated process to form the “Panel”type package. It needs the mold tool for encapsulation and the injectionof mold material. It is unlikely to control the surface of die andcompound at same level due to warp after heat curing the compound, theCMP process may be needed to polish the uneven surface. The cost istherefore increased.

Therefore, the present invention provides a FO-WLP structure with goodCTE performance and shrinkage size to overcome the aforementionedproblem and also provide the better board level reliability test oftemperature cycling.

SUMMARY OF THE INVENTION

The object of the present invention is to provide a WLP with good CTEperformance and shrinkage size.

The further object of the present invention is to provide a WLP with asubstrate having die receiving cavity for shrinking the device size.

The further object of the present invention is to provide a dielectriclayer formed on the die and the substrate and refill into a gap betweenthe die and the substrate to absorb thermal mechanical stress therebetween, wherein the dielectric layer includes an elastic dielectriclayer, a photosensitive layer, a silicone dielectric based layer,siloxane polymer (SINR) layer, a polyimides (PI) layer or silicone resinlayer.

The present invention provides a structure of package comprising asubstrate with a pre-formed die receiving cavity formed and/or terminalcontact metal pads (for FR5/BT substrate) within an upper surface of thesubstrate. A die is disposed within the die receiving cavity by adhesionand a dielectric layer formed on the die and the substrate. At least onere-distribution built up layer (RDL) is formed on the dielectric layerand coupled to the die via contact pad. Connecting structure, forexample, UBM is formed over the re-distribution built up layer and onthe terminal contact metal pads. Terminal Conductive bumps are coupledto the UBM.

The dielectric layer includes an elastic dielectric layer, siliconedielectric based material, BCB or PI. The silicone dielectric basedmaterial comprises siloxane polymers (SINR), Dow Corning WL-5000 series,or composites thereof. Alternatively, the dielectric layer comprises aphotosensitive layer. The dielectric layer is formed on the die and thesubstrate and refill into a gap between the die and the substrate toabsorb thermal stress there between, wherein the dielectric layerincludes an elastic dielectric layer, a photosensitive layer, a siloxanepolymer (SINR) layer, a polyimides (PI) layer or silicone resin layer.

The material of the substrate includes organic epoxy type FR4, FR5, BT(Bismaleimide Triazine epoxy), PCB (print circuit board), PI (Polyimidetype), alloy or metal. The alloy includes Alloy42 (42% Ni-58% Fe) orKovar (29% Ni-17% Co-54% Fe). Alternatively, the substrate could beglass, ceramic or silicon.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a cross-sectional view of a structure of fan-out WLPaccording to the present invention.

FIG. 2 illustrates a cross-sectional view of a structure of fan-out WLPaccording to the present invention.

FIG. 3 illustrates a cross-sectional view of a structure of fan-out WLPaccording to the present invention.

FIG. 4 illustrates a cross-sectional view of the combination of thesubstrate and the tool according to the present invention.

FIG. 5 illustrates a top view of the combination of the substrate andthe tool according to the present invention.

FIG. 6 illustrates a cross-sectional view of the combination of thepackage attached on the PCB or Mother Board according to the presentinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The invention will now be described in greater detail with preferredembodiments of the invention and illustrations attached. Nevertheless,it should be recognized that the preferred embodiments of the inventionis only for illustrating. Besides the preferred embodiment mentionedhere, present invention can be practiced in a wide range of otherembodiments besides those explicitly described, and the scope of thepresent invention is expressly not limited expect as specified in theaccompanying claims.

The present invention discloses a structure of WLP utilizing a substratehaving predetermined terminal contact metal pads 3 formed thereon and apre-formed cavity 4 formed into the substrate 2. A die is disposedwithin the die receiving cavity by adhesion. A photosensitive materialis coated over the die and the pre-formed substrate. Preferably, thematerial of the photosensitive material is formed of elastic material.

FIG. 1 illustrates a cross-sectional view of Fan-Out Wafer Level Package(FO-WLP) in accordance with one embodiment of the present invention. Asshown in the FIG. 1, the structure of FO-WLP includes a substrate 2having a terminal contact metal pads 3 (for organic substrate) and diereceiving cavity 4 formed therein to receive a die 6. The cavity 4 ispre-formed within the substrate 2. A cover 22 is formed under the lowersurface of the substrate 2 for laser mark or protection. The materialincludes epoxy.

The die 6 is disposed within the die receiving cavity 4 on the substrate2 and fixed by an adhesion material 8 (preferably, elastic basedmaterials). As know, contact pads (Bonding pads) 10 are formed on thedie 6. A photosensitive layer or dielectric layer 12 is formed over thedie 6 and filling into the space between the die 6 and the sidewalls ofthe cavity 4. Pluralities of openings are formed within the dielectriclayer 12 through the lithography process or exposure and developprocedure. The pluralities of openings are aligned to the contact padsor I/O pads 10 and terminal contact metal pads 3 (refer to FIG. 2),respectively. The RDL (re-distribution layer) 14, also referred to asconductive trace 14, is formed on the dielectric layer 12 by removing(seed layers) selected portions of metal layer formed over the layer 12,wherein the RDL 14 keeps electrically connected with the die 6 throughthe I/O pads 10 and terminal contact metal pads 3, A part of thematerial of the RDL will re-fills into the openings in the dielectriclayer 12. A protection layer 16 is formed to cover the RDL 14. Terminalpads 18 are located on the protection layer 16 and connected to the RDL14 and terminal contact metal pads 3 of substrate. A scribe line 28 isdefined between the units 2 for separating each unit 2, any there is nodielectric layer (optional).

The dielectric layer 12 is formed atop of the die 6 and substrate 2 andfills the space surrounding the die 6; due to the dielectric layer 12 iselastic property, it acts as buffer area can absorb the thermalmechanical stress between the die 6 and substrate 2 during temperaturecycling. The aforementioned structure constructs LGA type package. Analternative embodiment can be seen in FIG. 2, Conductive balls 20 areformed on the terminal pads 18. This type is called BGA type. The otherparts are similar to FIG. 1, therefore, the detailed description isomitted. The terminal pads 18 act as the UBM (under ball metal) underthe BGA scheme. Pluralities of terminal contact conductive pads 3 areformed on the upper surface of the substrate 2 and under the RDL 14.

Preferably, the material of the substrate 2 is organic substrate likesFR5, BT, PCB with defined cavity or Alloy42 with pre etching circuit.Preferably, the organic substrate with high Glass transition temperature(Tg) are epoxy type FR5 or BT (Bismaleimide triazine) type substrate.The Alloy42 is composed of 42% Ni and 58% Fe. Kovar can be used also,and it is composed of 29% Ni, 17% Co, 54% Fe. The glass, ceramic,silicon can be used as the substrate.

It is because that the CTE (X/Y direction) of the epoxy type organicsubstrate (FR5/BT) is around 16 and the CTE of the Tool of chipredistribution around is around 5 to 8 by employing the glass materialsas the tool. The FR5/BT can not return to original location after thetemperature cycling (near to Glass transition temperature Tg) thatcauses the die shift in panel form during the WLP process which needsseveral high temperature process. For example, the dielectric layersformation, the heat curing die attached materials etc., the followingprocess steps and tool are to make sure organic substrate can keep theoriginal location and no any warp happen during process.

Please refer to FIG. 3, the substrate could be round type such as wafertype, the diameter could be 200, 300 mm or higher. It could be employedfor rectangular type such as panel form. FIG. 3 illustrates thesubstrate 2 for the panel wafer form after process but beforesingulation. As can be seen from the drawings, the substrate 2 ispre-formed with cavities 4. In the upper portion of FIG. 4, the units ofFIG. 1 are arranged in a matrix form. A scribe line 28 is definedbetween the units 2 for separating each unit 2.

Please refer to FIG. 4, there is no cavity 4 formed at the peripheral(edge) area 42 of the substrate 2. A glass carrier tool 40 with adhesivematerial (preferably UV curing type) 44 formed at the peripheral area ofthe glass tool for (adhesion) handling organic substrate during WLPprocess. The lower portion of the FIG. 4 is the combination of the glasscarrier tool 40 and the substrate 2 after bonding and UV curing. FIG. 5shows that the edge area of substrate 2 does not include the die cavity,the periphery area will be used for sticking the glass carrier duringWLP process. The substrate will be adhered with glass carrier and itwill be stuck and hold the substrate during process. After the WLPprocess is completed, the area indicated by the dot line will be cutfrom the glass carrier, it means that the inner area defined by the dotline will be performed the sawing process for package singulation.

In one embodiment of the present invention, the dielectric layer 12 ispreferably an elastic dielectric material which is made by siliconedielectric based materials comprising siloxane polymers (SINR), DowCorning WL5000 series, and composites thereof. In another embodiment,the dielectric layer is made by a material comprising, polyimides (PI)or silicone resin. Preferably, it is a photosensitive layer for simpleprocess.

In one embodiment of the present invention, the elastic dielectric layeris a kind of material with CTE larger than 100 (ppm/° C.), elongationrate about 40 percent (preferably 30 percent-50 percent), and thehardness of the material is between plastic and rubber. The thickness ofthe elastic dielectric layer 18 depends on the stress accumulated in theRDL/dielectric layer interface during temperature cycling test.

Please refer to FIG. 6, it illustrates the major portions that associatewith the CTE issue. The silicon die (CTE is 2.3) is packaged inside thepackage. FR5 or BT organic epoxy type material (CTE˜16) is employed asthe substrate and its CTE is the same as the PCB or Mother Board. Thegap between the die and the substrate is filled with elastic materialsto absorb the thermal mechanical stress due to CTE mismatching (betweendie and the FR5/BT). Further, the dielectric layers 12 include elasticmaterials to absorb the stress between the die pads and the PCB. The RDLmetal is Cu/Au materials and the CTE is around 16 that is the same asthe PCB and organic substrate, and the UBM 18 of contact bump be locatedon the terminal contact metal pads 3 of substrate. The metal land of PCBis Cu, the CTE of Cu is around 16 that is match to the one of PCB. Fromthe description above, the present invention may provide excellent CTEsolution for the WLP.

Apparently, CTE matching issue under the build up layers (PCB andsubstrate) is solved by the present scheme and it provides betterreliability (no thermal stress in X/Y direction—on board) and theelastic DL is employed to absorb the Z direction stress. Only onematerial (Epoxy type) is involves the singulation. The gap between chipedge and cavity sidewall can be used to fill the elastic dielectricmaterials to absorb the mechanical/thermal stress.

In one embodiment of the invention, the material of the RDL 24 comprisesTi/Cu/Au alloy or Ti/Cu/Ni/Au alloy; the thickness of the RDL 24 isbetween 2 um_and_(—)15 um. The Ti/Cu alloy is formed by sputteringtechnique also as seed metal layers, and the Cu/Au or CU/Ni/Au alloy isformed by electroplating; exploiting the electro-plating process to formthe RDL can make the RDL thick enough to withstand CTE mismatchingduring temperature cycling. The metal pads 20 can be Al or Cu orcombination thereof. If the structure of FO-WLP utilizes SINR as theelastic dielectric layer and Cu as the RDL, according the stressanalysis not shown here, the stress accumulated in the RDL/dielectriclayer interface is reduced.

As shown in FIG. 1-3, the RDL 24 fans out of the die and communicatestoward the terminal pads 18. It is different from the prior arttechnology, the die 6 is received within the pre-formed cavity of thesubstrate, thereby reducing the thickness of the package. The prior artviolates the rule to reduce the die package thickness. The package ofthe present invention will be thinner than the prior art. Further, thesubstrate is pre-prepared before package. The cavity 4 ispre-determined. Thus, the throughput will be improved than ever. Thepresent invention discloses a fan-out WLP with reduced thickness andgood CTE performance.

The process for the present invention includes providing an alignmenttool with alignment pattern formed thereon. Then, the pattern glues isprinted on the tool (be used for sticking the surface of dice), followedby using pick and place fine alignment system with flip chip function tore-distribute the known good dies on the tool with desired pitch. Thepattern glues will stick the chips on the tool. Subsequently, the dieattached materials is printed on the die back side (preferably, theelastic based materials). Then, the panel bonder is used to bond thesubstrate on to die back side; the upper surface of substrate except thecavities also be stuck on the pattern glues, then vacuum curing andseparate the tool with panel wafer.

Alternatively, the die bonder machine with fine alignment is employed,and the die attached materials is dispensed on the cavity of substrate.The die is placed on to the cavity of substrate. The die attachedmaterials is thermally cured to ensure the die is attached on thesubstrate.

Once the die is re-distributed on the substrate, then, a clean upprocedure is performed to clean the dice surface by wet and/or dryclean. Next step is to coat the dielectric materials on the panel,followed by performing vacuum procedure to ensure there is no bubblewithin the panel. Subsequently, lithography process is performed to openvia (contact metal pads) and Al bonding pads and/or the scribe line(optional). Plasma clean step is then executed to clean the surface ofvia holes and Al bonding pads. Next step is to sputter Ti/Cu as seedmetal layers, and then Photo Resistor (PR) is coated over the dielectriclayer and seed metal layers for forming the patterns of redistributedmetal layers (RDL). Then, the electro plating is processed to form Cu/Auor Cu/Ni/Au as the RDL metal, followed by stripping the PR and metal wetetching to form the RDL metal trace. Subsequently, the next step is tocoat or print the top dielectric layer and to open the contact bump viato form the UBM and/or to open the scribe line (optional).

After the ball placement or solder paste printing, the heat re-flowprocedure is performed to re-flow on the substrate side (for BGA type).The testing is executed. Panel wafer level final testing is performed byusing vertical probe card. After the testing, the substrate is sawed tosingular the package into individual units. Then, the packages arerespectively picked and placed the package on the tray or tape and reel.

The advantages of the present invention are:

The process is simple for forming Panel wafer type and is easy tocontrol the roughness of panel surface. The thickness of panel (dieattached) is easy to be controlled and die shift issue will not occursduring process. The injection mold tool is omitted and warp and CMPpolish process will not be introduced either.

The substrate is pre-prepared with pre-form cavity and terminal contactmetal pads (for organic substrate); the size of cavity equal to (diesize+plus around 50 um to 100 um per/side; it can be used as stressbuffer releasing area by filling the elastic dielectric materials toabsorb the thermal stress due to the CTE difference between silicon dieand substrate (FR5/BT)). The packaging throughput will be increased(manufacturing cycle time was reduced) due to apply the simple build uplayers on top the surface of die. The terminal pads are formed on thesame surface to the dice active surface.

The dice placement process is the same as the current process. No corepaste (resin, epoxy compound, silicone rubber, etc.) filling isnecessary for the present invention. CTE mismatching issue is overcomeduring panel form process and the deepness between die and substrate FR4is only around ˜20-30 um (act as die attached thickness), the surfacelevel of die and substrate can be the same after the die is attached onthe cavities of substrate. Only silicone dielectric material (preferablySINR) is coated on the active surface and the substrate (preferably FR45or BT) surface. The contact pads are opened by using photo mask processonly due to the dielectric layer (SINR) is photosensitive layer foropening the contacting open. Vacuum process during SINR coating is usedto eliminate the bubble issue during filling the gap between die andside wall of cavity of substrate. The die attached material is printedon the back-side of dice before substrate be bonded together with dice(chips). The reliability for both package and board level is better thanever, especially, for the board level temperature cycling test, it wasdue to the CTE of substrate and PCB mother board are identical, hence,no thermal mechanical stress be applied on the solder bumps/balls; theprevious failure mode (solder ball crack) during temperature cycling onboard test were not obvious. The cost is low and the process is simple.It is easy to form the combo package (dual dice package).

Although preferred embodiments of the present invention have beendescribed, it will be understood by those skilled in the art that thepresent invention should not be limited to the described preferredembodiments. Rather, various changes and modifications can be madewithin the spirit and scope of the present invention, as defined by thefollowing claims.

1. A structure of package comprising: a substrate with a pre-formed diereceiving cavity and/or terminal contact pads formed within an uppersurface of said substrate; a die disposed within said die receivingcavity by adhesion; a dielectric layer formed on said die and saidsubstrate and refill into a gap between said die and said substrate toabsorb thermal mechanical stress there between, wherein said dielectriclayer includes an elastic dielectric layer, a photosensitive layer, asilicone dielectric based layer, a siloxane polymer (SINR) layer, apolyimides (PI) layer or silicone resin layer, a re-distribution layer(RDL) formed on said dielectric layer and coupled to said die; andpluralities of pads coupled to said RDL.
 2. The structure of claim 1,further comprising a conductive bump coupled to said pad.
 3. Thestructure of claim 1, wherein said RDL is made from an alloy comprisingTi/Cu/Au alloy or Ti/Cu/Ni/Au alloy.
 4. The structure of claim 1,wherein the material of said substrate includes epoxy type FR5 or FR4.5. The structure of claim 1, wherein the material of said substrateincludes BT, silicon, PCB (print circuit board) material, glass orceramic.
 6. The structure of claim 1, wherein the material of saidsubstrate includes alloy or metal.
 7. The structure of claim 6, whereinthe material of said substrate includes Alloy42 (42% Ni-58% Fe) or Kovar(29% Ni-17% Co-54% Fe).
 8. The structure of claim 1, further includes aprotection layer formed on said RDL.
 9. A method for formingsemiconductor device package comprising: providing a substrate with apre-formed die receiving cavity and/or terminal contact pads formedwithin an upper surface of said substrate; using a pick and place finealignment system to re-distribute known good dice on a carrier tool withdesired pitch, wherein said carrier tool includes adhesive material atthe periphery area of said carrier tool to adhere said substrate;attaching adhesive material on die back side; bonding said substrate onto said die back side, and curing then separating said tool from saidsubstrate; coating a dielectric layer on said die and substrate,followed by performing vacuum procedure; forming an opening to expose acontact pad of said die and/or substrate; forming at least oneconductive built up layer over said dielectric layer; forming acontacting structure over said at least one conductive built up layer;forming a protection layer over said at least one conductive built uplayer.
 10. The method of claim 9, further comprising forming aconductive bump coupled to said contacting structure.
 11. The method ofclaim 9, wherein said dielectric layer includes an elastic dielectriclayer, a photosensitive layer, a silicone dielectric based materiallayer, a polyimides (PI) layer or a silicone resin layer.
 12. The methodof claim 11, wherein said silicone dielectric based material comprisessiloxane polymers (SINR), Dow Corning WL5000 series, or the combinationthereof.
 13. The method of claim 9, wherein said at least one conductivebuilt up layer is made from an alloy comprising Ti/Cu/Au alloy orTi/Cu/Ni/Au alloy.
 14. The method of claim 9, wherein the material ofsaid substrate includes epoxy type FR5 or FR4.
 15. The method of claim9, wherein the material of said substrate includes BT, silicon, PCB(print circuit board) material, glass or ceramic.
 16. The method ofclaim 9, wherein the material of said substrate includes alloy or metal.17. The method of claim 16, wherein the material of said substrateincludes Alloy42 (42% Ni-58% Fe) or Kovar (29% Ni-17% Co-54% Fe). 18.The method of claim 9, wherein said carrier tool is made of glass.